1. Field of the Invention
The present invention relates to a semiconductor device including a logic circuit configured by MOS transistors, and particularly relates to a semiconductor device employing standby current reduction method for the purpose of reducing current in standby operation for a semiconductor memory device such as a DRAM (Dynamic Random Access Memory).
2. Description of the Related Art
In recent years, semiconductor memory devices such as DRAM have been often installed in mobile devices, and it becomes an important issue to reduce consumption current in standby operation. As a technique for such a reduction in consumption current, attention is directed toward standby current reduction method capable of suppressing sub-threshold current of a MOS transistor using a sub-power supply voltage VCT lower than a power supply voltage VCC and a sub-ground voltage VST higher than a ground voltage VSS. By applying the standby current reduction method to a multi-stage inverter circuit or the like in DRAM, the reduction in consumption current can be expected in standby operation (for example, see Japanese Laid-Open Patent Publication H11-31385).
A specific configuration example of a semiconductor device employing the standby current reduction method is shown in FIGS. 8 and 9. FIG. 8 shows a circuit configuration using MOS transistors corresponding to a two-stage inverter portion when configuring the multi-stage inverter circuit in the semiconductor device employing the standby current reduction method. In FIG. 8, the configuration in which an input signal IN is passed through the two-stage inverters so as to be output as an output signal OUT and the output signal OUT is low in standby operation. In the standby current reduction method, the power supply voltage VCC and the ground voltage VSS are supplied to MOS transistors being on, while the sub-power supply voltage VCT and the sub-ground voltage VST are supplied to MOS transistors being off, and it is thereby possible to suppress unnecessary sub-threshold current.
As shown in FIG. 8, a first-stage inverter includes a pair of a PMOS transistor P1 and an NMOS transistor N1 having commonly connected gates and commonly connected drains. Similarly, a second-stage inverter includes a pair of a PMOS transistor P2 and an NMOS transistor N2 having commonly connected gates and commonly connected drains. The input signal IN is applied to the gate of the first-stage, and the drain of the first-stage is connected to the gate of the second-stage so as to extract the signal OUT from the drain of the second-stage.
A PMOS transistor P3 is used as a driver on the P-channel side, and controls the power supply voltage VCC applied to the source by a control voltage Vgp applied to the gate, so that the sub-power supply voltage VCT lower than the power supply voltage VCC is generated at the drain. On the other hand, an NMOS transistor N3 is used as a driver on the N-channel side, and controls the ground voltage VSS applied to the source by a control voltage Vgn applied to the gate, so that the sub-ground voltage VST higher than the ground voltage VSS is generated at the drain.
In FIG. 8, a main power supply line L1 for supplying the power supply voltage VCC, a main ground line L2 for supplying the ground voltage VSS, a sub-power supply line L3 for supplying the sub-power supply voltage VCT, and a sub-ground line L4 for supplying the sub-ground voltage VST are formed. In standby operation, the input signal IN goes low, and the source of the PMOS transistor P1 being on in the first-stage is connected to the main power supply line L1, while the source of the NMOS transistor N1 being off in the first-stage is connected to the sub-ground line L4. Further, the source of the PMOS transistor P2 being off in the second-stage is connected to the sub-power supply line L3, while the source of the NMOS transistor N2 being on in the second-stage is connected to the main ground line L2.
FIG. 9 shows a layout corresponding to the circuit configuration of FIG. 8. The layout of FIG. 9 includes diffusion layers 101, 102 and 103 in which PMOS transistors P1, P2 and P3 are respectively formed, diffusion layers 104, 105 and 106 in which NMOS transistors N1, N2 and N3 are respectively formed, a gate wiring layer 111 connected to each gate electrode of the transistors, a source/drain wiring layer 112 in which wiring for each source/drain of the transistors is formed, and a wiring layer 113 in which various kinds of wiring including the main power supply line L1, the main ground line L2, the sub-power supply line L3 and the sub-ground line L4 are formed. The diffusion layers 101 to 106 and the source/drain wiring layer 112 are connected through a number of contacts 121, and different wiring layers are connected by vias 122.
In FIG. 9, two PMOS transistors P3 and two NMOS transistors N3 which constitute the drivers are respectively arranged in parallel with each other, which is different from the circuit configuration of FIG. 8. Actually, the numbers of PMOS transistors P3 and the NMOS transistors N3 to be arranged are appropriately determined according to the capability of each driver.
On the left side of FIG. 9, four diffusion layers 101, 102, 104 and 105 which are used to configure the two-stage inverters are formed in sizes corresponding to operation characteristics of the PMOS transistors P1 and P2 and the NMOS transistors N1 and N2, and it is necessary to arrange adjacent diffusion layers 101, 102, 104 and 105 so as to be spaced a predetermined distance apart from one another according to design rules. By this, the area occupied by the inverter portion is restricted in the layout of FIG. 9.
Further, on the right side of FIG. 9, two diffusion layers 103 and 106 which are used to configure the drivers are formed in sizes corresponding to the driving capability, and the extra size is needed in the lateral direction in the layout of FIG. 9. Thus, in the configuration employing the standby current reduction method, the layout area of the driver portion relative to the inverter portion cannot be negligible.
Further, when the standby current reduction method is not employed, only the main power supply line L1 and the main ground line L2 are required to be formed in the wiring layer 113 of FIG. 9. In contrast thereto, when the standby current reduction method is employed, the sub-power supply line L3 and the sub-ground line L4 are required to be formed in addition to the main power supply line L1 and the main ground line L2. Therefore, the area occupied by the wirings of the four power supply lines increases, resulting in a disadvantage in using the layout efficiently.
Thus, according to the conventional configuration employing the standby current reduction method, it is inevitable to increase the area for arranging the drivers and the wirings in the layout of the semiconductor device, and a problem arises that the entire chip size increases.